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STS-100 Synchronous Timing Module
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Features
* Suitable for Stratum 3 and 4 SONET or SDH Equipment Clocks (SEC) applications * Supports 14 individual inputs (LVDS, LVPECL, TTL) at Nx8 kHz multiples up to 155.52 MHz * 11 output reference clocks: 7xSEC(1.544MHz, 2.048MHz, 6.48 to 155.52MHz), 1BITS(1.544MHZ, 2.048MHZ), 64kHz/8kHz composite clock, 8 kHz frame sync, 2 kHz multi-frame sync. * Supports Free Run, Lock and Hold Over modes of operation. * Robust monitoring on all input clock sources * Automatic "hitless" switchover on loss of input. * Phase build-out for output clock phase continuity during input switch over or mode transitions. * Supports Microprocessor interface - Intel, Motorola, Multiplexed, Serial and EEPROM * Programmable wander/jitter tracking/attenuation 0.1Hz to 20Hz * Supports master/Slave configuration and hot/standby redundancy.
Bulletin Page Revision Date Issued By
TM026 1 of 8 P03 25 APR 06 ENG
* 3.3V Operation * Meets Telcordia specifications * ROHS-5 Compliant
Application
The STS-100 module provides Synchronous Equipment Timing Source (SETS) function in a SONET/ SDH network element. It generates SONET/SDH equipment clocks (SEC) and frame synchronization clocks. The module supports Free run, Locked and Holdover modes of operations. The module supports 14 input clocks and generates 11 different outputs. The module also supports master/slave configuration, which provides protection against single STS-100 failure. This module is incorporated with a microprocessor port, which provides access to the internal registers. The STS-100 module is a platform that is designed to support easy installation and upgrade paths of the ACS8530 SETS chip from Semtech. For timing diagrams and additional details, please refer to the ACS8530 data sheet. For register assignments, please refer to the ACS8530 data sheet. This product is ROHS-5 compliant. ROHS-5 indicates that this product is ROHS compliant except for lead from those manufacturers wishing to take the lead exemption.
Functional Block Diagram
12.8 MHz OCXO
AMI (64 kHz/8kHz) AMI (64 kHz/8 kHz) 2kMFr Sync Input 6.48 MHz Input Interrupt RDY 8kHz FrSync w/ 50:50 MSR 2kHz MFrSync w/ 50:50 MSR AMI 64 kHz/8 kHz Output
2 Configurable LVDS/PECL Inputs up to 155.52 MHz
ACS8530 SETS chip
19.44 MHz CMOS Output 38.88 MHz CMOS Output 77.76 MHz CMOS Output 2 Selectable LVDS/PECLOutputs 1@ 1.544 - 311.04 MHz 1@ 1.544 - 155.52 MHz
10 TTL/CMOS Configurable References up to 100 MHz
7 Bit Address 3 Selectable TTL/CMOS Outputs 1@1.544 - 25.92 MHz 1@1.544 - 51.84 MHz 1@1.544 - 2.048 MHz
8 Bit Data
Control Inputs
Pin Outs
Figure 2
Two QTH-030-03-H-D-A-K-TR connectors from SAMTEC(R) are used on the STS-100 Module. The mating Part# is QSH-030-01-H-D-A-K-TR.
Data Sheet #: TM026
Page 2 of 8
Rev: P03
Date: 4/25/06
(c) Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Absolute Maximum Rating
Table 1
Symbol VCC VI VO Ts Parameter Power Supply Voltage Input Voltage Output Voltage Storage Temperature -40 Minimum -0.5 Nominal Maximum 3.6 3.6 3.6 85 Units Volts Volts Volts C Notes
Recommended Operating Conditions
Table 2
Symbol Vcc IIN TOP VIH VIL VIH VIL VIH VIL Parameter Power Supply Voltage Power Supply Current (Power-up) (Typical) Operating Temperature High level input voltage - TTL/CMOS Low level input voltage - TTL/CMOS High level input voltage - AMI Low level input voltage - AMI High level input voltage - LVPECL/LVDS Low level input voltage - LVPECL/LVDS 0 Minimum 3.0 Nominal 3.3 650 450 Maximum 3.6 750 550 70 Units Volts mA mA C Notes
Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS
DC Characteristics - Outputs
Table 3
Symbol VOH VOL VOH VOL VOH VOL Parameter High level output voltage, TTL/CMOS Low level output voltage, TTL/CMOS High level output voltage, AMI Low level output voltage, AMI High level output voltage, LVPECL/LVDS Low level output voltage, LVPECL/LVDS Minimum Nominal Maximum Units Notes Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS Refer to Semtech's data sheet for ACS8530 SETS
Specifications
Table 4
Parameter Input Frequency Range Output Frequency Range Timing Reference Inputs Jitter, Wander and Phase Transient Tolerances Wander Generation Wander Transfer Jitter Generation Jitter Transfer Phase Transients Free Run Accuracy Pull-in/ Hold-in Range Specifications 2kHz,8kHz,64kHz,1.544MHz, 2.048MHz, 6.48MHz-155.52MHz 2kHz,8kHz,64kHz,1.544MHz, 2.048MHz, 6.48MHz-311.04MHz GR-1244-CORE 3.2.1 GR-1244-CORE 4.2-4.4, GR-253-CORE 5.4.4.3.6 GR-1244-CORE 5.3, GR-253-CORE 5.4.4.3.2 GR-1244-CORE 5.4 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.3 GR-1244-CORE 5.5, GR-253-CORE 5.6.2.1 GR-1244-CORE 5.6, GR-253-CORE 5.4.4.3.3 4.6 ppm 17 ppm from Free Run frequency Notes
Data Sheet #: TM026
Page 3 of 8
Rev: P03
Date: 4/25/06
(c) Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Connector S1 Table 5
PIN
1,3,5,7, 9,11,13 2 4 6 8 10 14 17,19,21 23,25,27 29,31 16 18 20 22 35, 37, 39 41 43 45 47 49 53, 54, 55, 56 61, 62, 63, 64 12, 15, 24, 26, 28, 30, 32, 33, 34, 36, 38, 40, 42, 44, 46, 48, 50, 51, 52, 57, 58, 59, 60
SYMBOL
A[0:6] CSB WRB RDB ALE RDY PORB AD[0:7] MSTSLVB INTRPT SRCSW SONSDHB UPSEL[0:2] TRST TCK TDO TDI TMS Vcc GND
I/O
I I I I I O I
DESCRIPTION
Address bus for microprocessor interface, A[0} is SDI in serial interface mode Chip Select (Active Low) Write (Active Low) Read (Active Low) Address latch enable. This pin acts as SCLK in serial mode. Ready/Data acknowledge Power on Reset (Active Low) Address/Data multiplexed address/data depending on microprocessor mode selection. AD[0] is SDO in serial mode
I O I I I I I O I I
Master/Slave select. Sets initial power up state Active high software interrupt Source switching. Force fast source switching. SONET/SDH frequency select. Sets initial power up state Configures the input for a particular microprocessor type. Tri-State input JTAG TCK input JTAG TDO output JTAG TDI input JTAG TMS output 3.3V Input Ground
NC
No Connect
Data Sheet #: TM026
Page 4 of 8
Rev: P03
Date: 4/25/06
(c) Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Connector S2 Table 6
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 31 33 35 37 39 41 21, 23, 25, 27, 29, 43, 45, 47, 49, 51, 53, 55, 57, 58, 59, 60
SYMBOL
REFIN1 REFOUT1 REFIN2 REFOUT2 REFIN3 REFOUT3 REFIN4 REFOUT4 REFIN5 REFOUT5 REFIN6 REFOUT6 REFIN7 REFOUT7 REFIN8 REFOUT8 REFIN9 SYNCOUT REFIN10 CLKOUT SYNC2K DOUT1_P DOUT1_N DOUT2_P DOUT2_N DOUT3_P DOUT3_N DOUT4_P DOUT4_N DOUT5_P DOUT5_N DOUT6_P DOUT6_N DOUT7_P DOUT7_N DOUT8_P DOUT8_N DIN1_P DIN1_N DIN2_P DIN2_N DIN3_P DIN3_N
I/O
I O I O I O I O I O I O I O I O I 0 I O I O O O O O O
IO Type
TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS AMI AMI LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS
DESCRIPTION
Input Reference Output Reference Input Reference Output Reference Input Reference Output Reference Input Reference Output Reference Input Reference Output Reference Input Reference Output Reference Input Reference (I3 input on ACS8530 SETS) (TO1 output on ACS8530 SETS) (I4 input on ACS8530 SETS) (TO2 output on ACS8530 SETS) (I7 input on ACS8530 SETS) (TO3 output on ACS8530 SETS) (I8 input on ACS8530 SETS) (TO4 output on ACS8530 SETS) (I9 input on ACS8530 SETS) (TO5 output on ACS8530 SETS) (I10 input on ACS8530 SETS) (TO9 output on ACS8530 SETS) (I11 input on ACS8530 SETS)
8 kHZ Frame SYNC output Input Reference (I13 input on ACS8530 SETS)
2 kHz Multi-Frame SYNC output Input Reference No Connect Input Reference Onboard oscillator output Sychronized to a 2 kHz multi-frame signal from partner STS-100A in a rededundancy system AMI Output AMI Output Differential Output Differential Ouput Differential Ouput Differential Ouput No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect No Connect (TO6 pins on ACS8530 SETS) (TO6 pins on ACS8530 SETS) (TO7 pins on ACS8530 SETS) (TO7 pins on ACS8530 SETS) (I14 input on ACS8530 SETS)
I I I I I I
AMI AMI LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS LVPECL/LVDS
AMI Input AMI Input Differential Input Differential Input Differential Input Differential Input
(I1 input on ACS8530 SETS) (I2 input on ACS8530 SETS) (I5 pins on ACS8530 SETS) (I5 pins on ACS8530 SETS) (I6 pins on ACS8530 SETS) (I6 pins on ACS8530 SETS)
NC
No Connect
Data Sheet #: TM026
Page 5 of 8
Rev: P03
Date: 4/25/06
(c) Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Microprocessor Interface
The STS-100 has a microprocessor interface incorporated into the module. The module can be configured to function in the modes listed in Table 2. The module is configured by using pins UPSEL[2:0].
Table 7
UPSEL[2:0] 000 001 010 011 100 101 110 111 MODE Off EEPROM Multiplexed INTEL MOTOROLA Serial Off Off
MOTOROLA mode: Parallel data + address. Compatible with 68x0 type bus. INTEL mode: Parallel data + address. Compatible with 80x86 type bus. Multiplexed mode: Data/address. Mode is suitable for microprocessors, which share bus signals between data and address. Serial mode: Compatible with serial interface. EEPROM mode: This mode is suitable for use with an EEPROM, in which configuration information is stored (one way communication- status information not accessible). Note: For timing diagrams and additional details, please refer to the ACS8530 data sheet.
Package Dimensions
Maximum Board Dimension: L x W x H = 2" x 2" x 0.5"
Fig 3
Data Sheet #: TM026
Page 6 of 8
Rev: P03
Date: 4/25/06
(c) Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended Connector Placement and Component Keep Out Area
Fig 4
2.0000 [50.80mm] 1.8900 [48.01mm]
1.3620 [34.59mm]
S1
01 02
S2
01 02
59
60
59
60
.5695 [14.47mm] O.1800 [O4.57mm] Copper Pad
.1100 [2.79mm] O.1040 [O2.64mm] Finished Hole .0000 [0.00mm] .3150 [8.00mm] 1.8450 [46.86mm] 2.0000 [50.80mm]
.1108 [2.81 mm] .7925 [20.13 mm]
.1100 [2.79mm]
Recommended Connector Footprint Dimensions
Fig 5
.1000 [2.54 mm]
.0078 [0.20 mm]
.0895 [2.27 mm]
01
02
.1925 [4.89 mm]
.0197 [0.50 mm]
.0110 [0.28 mm]
59
.1850 [4.70 mm]
60
.1128 [2.87 mm]
.0170 [0.43 mm] .3151 [8.00 mm]
.5711 [14.50 mm]
O.0 40 0 [O 1.0 2m m]
Samtec PN: QSH-030-01-H-D-A-K-TR
Data Sheet #: TM026
.6350 [16.13 mm]
.2500 [6.35 mm]
1.8900 [48.01mm]
Page 7 of 8
Rev: P03
Date: 4/25/06
(c) Copyright 2006 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630- 851- 4722 Fax: 630- 851- 5040 www.conwin.com
Revision P00 P01 P02 P03
Revision Date 8/27/01 8/9/02 10/10/02 4/25/06
Note Preliminary Product Release Updated current specs & SETS PN Added millimeter dimensions to mechancial drawings. Added ROHS-5/6 Compliance

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